1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming diffusion breaks on integrated circuit (IC) products comprised of FinFET devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
A conventional FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of fin-formation trenches 13, three illustrative fins 14, a gate 16, a sidewall spacer 18 and a gate cap layer 20. An insulating material 17 provides electrical isolation between the fins 14. The gate 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the gate length (GL) of the device, i.e., the direction of current travel in the device 10 when it is operational. The gate width (GW) of the device 10 is orthogonal to the gate length direction. The portions of the fins 14 covered by the gate 16 are the channel region of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10. Typically, additional epi semiconductor material (not shown) is formed on the portions of the fins 14 in the source/drain regions. A trench may or may not be formed in the fins 14 prior to the formation of the epi material. The epi material may be formed so as to result in merged or un-merged epi material in the source/drain regions.
Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins. As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm.
However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially etch the fin-formation trenches 13 in the substrate 12 to define multiple “fins” that extend across the entire substrate 12 (or area of the substrate where FinFET devices will be formed), and thereafter remove portions of the fins where isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform environment in which the etching process that forms the trenches 13 is performed. After the trenches 13 are formed, some portion of some of the fins 14 must be removed to create room for or define the spaces where isolation regions will ultimately be formed.
FIG. 1B is a simplistic plan view of a plurality of fins that have been initially formed in the substrate 12. Also depicted in dashed lines are a plurality of gates that will eventually be formed across the fins after portions of the fins are cut and removed.
As shown in FIG. 1C, a FinFET device will eventually be formed that has an active gate structure. Also depicted are illustrative “dummy” gate structures (for this particular active FinFET device) that are positioned laterally adjacent the active gate structure. The gate structures are still depicted in dashed lines as they have not yet been formed. Additionally, it should be noted that the “dummy” gate structures are dummy or inactive gate structures as it relates to the active FinFET device, portions of these dummy gates may constitute active gates for other FinFET devices formed in other regions of the substrate. Also depicted are two openings 22 in a patterned masking layer, e.g., a patterned layer of photoresist that has been formed above the fins. The patterned masking layer may sometimes be referred to as a “fin-cut” mask. The openings 22 in the patterned masking layer correspond to portions of the fins that are to be cut and removed so as to make room for isolation structures on opposite sides of the active FinFET device.
FIG. 1D depicts the product after an etching process was performed to remove the portions of the fins exposed by the openings 22 in the patterned masking layer and after the patterned masking layer was removed. As indicated in the dashed line regions 24, portions of the fins have been removed to make room for the isolation structures.
FIG. 1E depicts the product at a later stage of fabrication wherein the gates have been formed across the fins. As depicted in the dashed line regions 26, by performing the fin cutting process before the gates are formed, there is significant risk that the gate passing above the openings 24 (see FIG. 1D) will not cover the exposed ends of the fins that were cut. As an example, it may be extremely difficult to accurately align the openings 22 in the fin cut mask with the precise location where the fins are to be removed and where the gate will subsequently be formed. Additionally, the actual size of the opening 24 in the fins may be larger or smaller than a target size due to etching process variabilities.
As a result of the situation depicted in FIG. 1E, when the additional epi semiconductor material is formed on the exposed portions of the fins not covered by the gates, the epi material formed on fins that were cut may not be as uniform as epi material that is formed on other un-cut portions of the fins. For example, the epi material formed on such devices may have a faceted edge and a smaller volume of epi material as compared to what was anticipated by the design process. Formation of such non-uniform epi material on the source/drain regions of FinFET devices can lead to reduced performance of such devices relative to what is anticipated by the design process which, in turn, can lead to an overall decrease in the performance capabilities of the integrated circuit product.
The present disclosure is directed to methods of forming diffusion breaks on IC products comprised of FinFET devices that may solve or reduce one or more of the problems identified above.